1. Field of the Invention
The present invention relates to a D/A conversion technique for converting digital signals to analog signals, and a target of the present invention is, for example, a D/A conversion circuit or the like for use in a circuit that drives signal lines in a pixel array substrate such as a liquid crystal display panel.
2. Related Background Art
A liquid crystal display device has a pixel array substrate in which a plurality of signal lines and scanning lines are arranged, and a drive circuit substrate in which a drive circuit for driving the signal lines and the scanning lines is formed. To reduce a mounting area, there are a case where a part of the drive circuit is formed in the pixel array substrate, and a case where the drive circuit is formed in a chip. Since the chip usually operates in a digital manner, pixel data is also treated in a digital signal state in the chip.
On the other hand, an analog pixel voltage is supplied to each signal line in the pixel array substrate so that gradation display can be accomplished. Therefore, the drive circuit is usually provided with a D/A conversion circuit for converting digital pixel data to the analog pixel voltage.
FIG. 1 is a circuit diagram of a conventional D/A conversion circuit provided in a signal line drive circuit of the liquid crystal display device. The D/A conversion circuit of FIG. 1 is equipped with an analog reference power supply 1, an output buffer 2 and a multiplexer 3, and an analog output VOUT outputted from the output buffer 2 is supplied to the corresponding signal line.
Each signal line is provided with the output buffer 2 and the multiplexer 3, respectively, and the analog reference power supply 1 is often shared. Usually, the plurality (e.g., 300 sets) of output buffers 2 and multiplexers 3 are collectively formed in an LSI chip.
The analog reference power supply 1 divides a power supply voltage VDD into resistance voltages so as to output a plurality of different voltages. The multiplexer 3 selects any one of the voltages outputted from the analog reference power supply 1 in accordance with a logic of digital pixel data D1 to D3 inputted from the outside. The output buffer 2 buffers the voltage outputted from the multiplexer 3, i.e., outputs a voltage that an impedance is converted. The output of the output buffer 2 is supplied to a pixel array substrate (not shown) outside the LSI chip.
FIG. 1 shows an example in which the number of bits of the digital pixel data D1 to D3 is three, and the multiplexer 3 selects one from eight types of voltages outputted from the analog reference power supply 1.
The multiplexer 3 has NAND gates G1 to G8, inverters IV1 to IV3, and switches SW11 to SW18. The inverters IV1 to IV3 are provided for each bit of the digital pixel data D1 to D3, and the switches SW11 to SW18 are provided for the NAND gates G1 to G8, respectively.
FIG. 2 is a diagram explaining voltage selection of the multiplexer 3. As shown in the drawing, the multiplexer 3 selects different voltages in accordance with a bit string of the digital pixel data D1 to D3. For example, when the bit string of the digital pixel data D1 to D3 is (0, 0, 0), an output of the NAND gate G8 of FIG. 1 is placed in a low level; as a result, the switch SW8 is turned on, and voltage V8 is supplied to the output buffer 2.
The D/A conversion circuit of FIG. 1 has a defect that the voltage outputted from the analog reference power supply 1 fluctuates. The defect will be described hereinafter in detail.
Here, a case where the voltages V1 and V8 are alternately selected from the voltages outputted from the analog reference power supply 1 of FIG. 1 will be described.
An equivalent input parasitic capacitor C1 is attached to an input terminal of the output buffer 2, and the input parasitic capacitor C1 is charged with an electric charge corresponding to the voltage selected by the multiplexer 3. For example, when the bit string of the digital pixel data D1 to D3 inputted to the multiplexer 3 is (1, 1, 1), the voltage V1 which is a maximum voltage is supplied to the output buffer 2, and the parasitic capacitor C1 is charged by the voltage V1. FIG. 1 shows an electric charging route with a solid-line arrow.
Subsequently, when the bit string of the digital pixel data D1 to D3 changes to (0, 0, 0), the voltage V8 which is a minimum voltage is supplied to the output buffer 2. Immediately before the bit string changes to (0, 0, 0), the parasitic capacitor C1 is charged with the voltage V1. Therefore, the electric charge added to the parasitic capacitor C1 is discharged through a route of a dotted line of FIG. 1.
Such movement of the electric charge can be treated as a direct current, and the direct current can be represented by equation (1).
I=Cx(V8xe2x88x92V1)/Txe2x80x83xe2x80x83(1)
In the equation (1), T denotes a period in which the voltage is switched over. The shorter the period is, the more direct current flows in the analog reference power supply. For example, when a frequency as an inverse number of T is set to F, the following equation (2) is established:
I=Cx(V8xe2x88x92V1)xc3x97Fxe2x80x83xe2x80x83(2)
In this manner, when the voltage selected by the multiplexer 3 changes to a high voltage from a low voltage, the input parasitic capacitor C1 of the output buffer 2 is charged. Conversely, when the voltage selected by the multiplexer 3 changes to a low voltage from a high voltage, the input parasitic capacitor of the output buffer 2 is discharged.
The electric current for charging/discharging the input parasitic capacitor C1 flows the analog reference power supply 1. That is, when the voltage selected by the multiplexer 3 changes to a high voltage from a low voltage, the charging current flows to the input parasitic capacitor C1 from the analog reference power supply 1, and the output voltage of the analog reference power supply 1 is lowered. Conversely, when the voltage selected by the multiplexer 3 changes to a low voltage from a high voltage, the current discharged from the input parasitic capacitor C1 flows into the analog reference power supply 1, and the output voltage of the analog reference power supply 1 is raised.
When the output voltage of the analog reference power supply 1 fluctuates, the analog output VOUT outputted from the D/A conversion circuit of FIG. 1 also fluctuates, and precision of D/A conversion is worsened. Therefore, when such D/A conversion circuit is used in the signal line drive circuit of the liquid crystal display device, no desired analog pixel voltage is supplied to the signal line, and display quality is worsened. Specifically, an influence of a specific display pattern is exerted, and cross talk occurs. Moreover, even when the analog reference power supply 1 of FIG. 1 is provided inside the LSI chip, the similar problem arises.
The D/A conversion circuit of so-called resistance dividing type has been described above in which a plurality of different voltages are outputted from a plurality of resistances connected in series. In a D/A conversion circuit of so-called capacity dividing type in which a plurality of different voltages are outputted from a plurality of capacitors connected in series or parallel, a plurality of capacitors have to be charged/discharged directly from the analog reference power supply. Therefore, as compared with the resistance dividing type, the electric current flowing through the analog reference power supply is increased, and the output voltage of the analog reference power supply fluctuates more largely. Furthermore, the cross talk by the influence of the specific display pattern also becomes larger as compared with that of the resistance dividing type.
The present invention has been developed in consideration of the above-described respects, and an object thereof is to provide a D/A conversion circuit which can perform D/A conversion at high speed and with high precision.
To attain the above object, a D/A conversion circuit provided with an analog reference power supply for using a first power supply voltage as a drive voltage and outputting a plurality of different voltages,
a voltage selecting circuit for selecting one voltage of voltages correlated with the plurality of different voltages, and
an output buffer for converting impedance of the voltage selected by the voltage selecting circuit, comprises:
a charging/discharging voltage generating circuit for using a second power supply voltage as the drive voltage and outputting voltages correlated with the output voltages of the analog reference power supply; and
a current switchover circuit for switching a direction in which a current flows in such a manner that a charging/discharging current of an input parasitic capacitor of the output buffer passes through the charging/discharging voltage generating circuit within a predetermined period after a bit string of digital data changes, and the charging/discharging current passes through the analog reference power supply after the predetermined period elapses.
According to the present invention, since the charging/discharging voltage generating circuit is provided in such a manner that the current for charging/discharging the input parasitic capacitor of the output buffer of the D/A conversion circuit fails to flow through the analog reference power supply, the output voltage of the analog reference power supply is prevented from fluctuating, and the precision of the D/A conversion can be improved. Moreover, by lowering an output impedance of the charging/discharging voltage generating circuit, it is possible to charge and discharge the input parasitic capacitor of the output buffer at high speed, and to perform the D/A conversion at high speed. Particularly, when the D/A conversion of a capacity dividing type is performed, the charging/discharging current during the D/A conversion is large. Therefore, by providing the charging/discharging voltage generating circuit, the fluctuation of the output voltage of the analog reference power supply can surely be suppressed, and the D/A conversion can be performed at higher speed and with higher precision than the conventional art.